Search - vhdl xilinx

[Other] chinese_version_Verilog_HDL_lecture

Description: 中文版Verilog HDL简明教程第1章简介第2章 HDL指南第3章 Verilog语言要素第4章表达式第5章门电平模型化 -Chinese version of Verilog HDL Concise Guide to Chapter 1 Introduction Chapter 2 HDL Guide, Chapter 3 Verilog language factor expression Chapter 4 Chapter 5 gate-level modeling
Platform: | Size: 88064 | Author: 王光辉 | Hits:

[VHDL-FPGA-Verilog] SS7160.ZIP

Description: 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
Platform: | Size: 720896 | Author: 王珏 | Hits:

[Other] taxiwork

Description: 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠，应用于实际当中有较好的实用价值和较高的可行性。-introduced FPGA-based multifunctional taxi meter circuit design. The design using programmable logic device FPGA ASIC design, and for the super-high-speed VHDL hardware description language in the company Xilinx Spartan II Series 2 sc 200PQ208-5 chip programming of the control system as a whole, Automatic control the entire system from four modules : a seconds-frequency module, control module, metrology modules and decoding module. The design not only achieved a taxi showed Billing functions, Multifunctional its performance through its keypad revealed taxi taking the cumulative total journey of the passengers took the set time. Program, log, billing is accurate, reliable and practical application of them have good practical value and the higher the possibility.
Platform: | Size: 9216 | Author: 柑佬 | Hits:

[VHDL-FPGA-Verilog] xapp616

Description: A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilog] S3Demo

Description: 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Platform: | Size: 291840 | Author: 计算机 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] ledleft

Description: xilinx的SPARTAN-3E入门开发板实例根据官方公布的led移动范例改写。原范例仅提供了源代码、烧写文件以及dos窗口下使用的烧写bat文件。本实例采用了ise7.1i创建，在ise下重建整个工程，有助于初学者理解使用。-xilinx the SPARTAN-3E portal development board examples According to the official announcement led to the mobile Examples rewritten. Original examples provided only source code, dos burning documents and the use of the window of burning bat documents. The examples used ise7.1i creation, the redevelopment of the entire ise project will help beginners understand the use.
Platform: | Size: 393216 | Author: 韩兆伟 | Hits:

[VHDL-FPGA-Verilog] labsolutions

Description: Xilinx的培训教程的源码 virtex-Xilinx training guides source virtex
Platform: | Size: 14724096 | Author: jihuijie | Hits:

[Software Engineering] ise_tutarial

Description: xilinx培训教程讲义，好几个ppt，讲解十分详细-xilinx Training Guide overhead, several ppt, on the very detailed
Platform: | Size: 12367872 | Author: jihuijie | Hits:

[VHDL-FPGA-Verilog] I2C_loader

Description: 用FPGA做主控制器，对IIC从设备配置参数的源程序。Xilinx提供-FPGA master controller, right from the IIC equipment configuration parameters of the source. Xilinx offer
Platform: | Size: 93184 | Author: cloud | Hits:

[Other] lab4ppc

Description: 嵌入式教程：Xilinx Spartan3e 开发环境：EDK 实验教程4：Writing Basic Software Applications -Embedded Tutorial : Xilinx Spartan3e development environment : EDK experimental Guide 4 : Writing Basic Software Applications
Platform: | Size: 1597440 | Author: David | Hits:

[VHDL-FPGA-Verilog] bujindianjiVHDL

Description:
Platform: | Size: 5120 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] sampleVHDL

Description: 采样等精度测量的VHDL程序．．在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
Platform: | Size: 122880 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] chipscope_vhdl_fpga_xilinx

Description:
Platform: | Size: 381952 | Author: 张红静 | Hits:

[VHDL-FPGA-Verilog] ClockDiv

Description: 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
Platform: | Size: 774144 | Author: 刘小军 | Hits:

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